Hello. As for Harvard vs Von Neumann architecture, I read that Harvard has one memory for data and instructions while V.N has two different memory systems, one for data and one for instructions.
I don’t quite understand this difference. What specifically is the difference between **instructions and data**? Aren’t all instructions data? And what kind of memory are we talking about here? RAM or CPU cache?
Thank you.
In: Technology
You’ve got the architectures switched. The von Neumann architecture makes no distinction between data and instruction memory while the Harvard architecture does.
Why instructions and data may be separated is that in early computers the instructions were stored on punched-cards or tape and working data was stored in another format. In fact, many early computers couldn’t modify the code they were running in any form and thus it didn’t make sense for that code to be part of the *limited* memory space available.
These architectures were defined before CPU caches or even RAM that was entirely separate from the CPU were a thing.
Additionally the term “Harvard architecture” was used to describe some early computers built at Harvard University, but years after the fact, by people not associated with Harvard.
You have these the wrong way around. Von Neumann architecture have a shared instruction/data bus while a Harvard architecture have a separate instruction bus and data bus. The difference here is how the processor interact with the rest of the system, including ram, hard disks and network. In a processor there are two different processes that reads data. The processing unit reads and writes data in order to process it. This could be from memory or it could be from the PCIe bus depending on the address. But there is also the control unit which fetches the next instruction to be executed. The control unit and the processing unit can run in parallel.
In a Harvard architecture the control unit have a dedicated bus to fetch the instructions. So you have separate cpu cache and separate memory for instructions. Obviously there needs to be a way to load programs into the instruction memory but that is out of scope here. In a Von Neumann architecture however the control unit will “hijack” the bus used by the processing unit and fetch the instructions using the same cache and memory as the data. The immediate issue you might see is that the processing might have to wait. If a processing unit wants to read some data from memory it might not be able to because the processing unit is currently reading the next instruction. So you may get some slowdown. But you only need one memory controller so it becomes a simpler system. The Harvard architecture however does have some advantages within security. You can more carefully control how the applications are loaded and either not allow reprogramming the computer or implement signature checks when loading applications.
These architectures were very early architectures from the time when computers were purpose built by a handful of people placing individual transistors, or even vacuum tubes. There were very few computers built to these exact architectures. Most computers are a mix of these concepts. For example the Intel 4004 used a shared memory bus like in a Von Neumann architecture but based on the timing it would be sent to either RAM or ROM so they got the effect of a Harvard architecture. Modern PC processors usually have a Harvard architecture in the core with separate busses and caches but then at some point the busses merge together like in a Von Neumann architecture. But a lot of embedded devices implement a pure Harvard architecture.
Well, let’s use a cooking analogy. In one architecture, you keep your recipes in a cabinet and your raw ingredients in a pantry. In the other one, ingredients and individual steps from the recipe are in the pantry together (and interleaved).
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