So as far as I understand Random Access Memory lets us access any stored in it data regardless where it’s stored and with the same speed.
I just don’t understand what makes that physically possible. Data is being transfered through electrons at approximately the speed of light through the wires. But how do you connect the wires to access all of the data everywhere in RAM at the same time?
Is the data being broken down into bits over all the RAM units – making the data collection process longer as you have to gather all the data particles or is there something I’m missing.
If I got any of my facts wrong feel free to correct me.
In: 7
If you can accept that we can use transistors to make AND, OR, and NOT gates, then I can explain it quite well, I think. If not, or if you’re not innately familiar with the exact function of those gates, it will take some more explaining and a lot of diagrams.
So first off, if I use the NOT gate to invert the output of an OR gate, we get a NOR gate. A NOR B is only true if both A and B are false (or I guess since we’re dealing with electrical voltages, replace true with high and false with low). If I take two nor gates and one of their inputs is tied to the output of the other, we have what’s called an SR latch (short for set/reset). If you raise the voltage of the free input on one of the NOR gates, it doesn’t matter what the other input (tied to the output of the other gate), because if either input to a NOR is high then the output must be low. But if it’s low, then that feeds into the second NOR gates which now sees both low signals and raises its output high. This high output is fed back into the first NOR gates which continues to hold it low even after you remove the input on the free leg. This is stable and considered set.
The logic is symmetric, if you raise the free input on the second NOR gate, it will swap states and the high output will turn low and the low output will turn high, but this is also stable when the free input is removed. So we can set and reset the latch which allows us to store either a high or low signals as long as there’s power. The NOT gate on each OR requires power to work, so as soon as power is removed, you loose all the data stored in RAM. But, how do we access it?
Let’s say we have an address of 3 bits (meaning we can store up to 8 bits in RAM… Well, actually, we can just copy and paste the whole circuit 8 times for every bit and connect each of the 8 outputs to a different bit of the bus, giving us 8 bytes of data to store in RAM). So our address runs from low low low (000) to high high high (111 in binary).
Let’s say we want to access address 5 (101 in binary). The exact circuit we want to implement is B1 AND NOT B2 AND B3 AND Dx (where Bx are the 3 bits of the address and Dx are the data bits 1 through 8 for the 8 bits stored at that address… Btw, I’m choosing to start counting at 1 instead of 0). Notice that if the first part of the circuit (B1 AND B2 AND B3) is true, then the output becomes whatever the data is. Dx AND high is high if Dx is high and low if Dx is low. So we’re just reading the data. Notice that if B1 is not 1 or B2 is not 0 or B3 is not 1 then the AND condition is broken, and the output is always low regardless of what’s in Dx. So we will not be able to read whatever is stored in Dx unless the address is exactly 101.
Repeat this circuit for all 8 possible addresses and let’s.call these functions F1-F8. Then we just OR them all together (F1 OR F2 OR… OR F8). Since 7 out of the 8 functions will be forced low (because the address isn’t exactly right) the the output of this 8-way or gate is whatever the 8th circuit will be. And remember, that one cell that does match the address will just output whatever Dx is. So the output of our 8-way OR gate is Dx.
If you change the address you give to RAM, the value in that cell will be put on the output as fast as all the transistors can flip states. We don’t have to worry about waiting for the disk to spin to the right location because there is already a physical path to every single bit in RAM just waiting to be accessed. All the bits we don’t care about are ignored because the address selection circuit forces them low when the address doesn’t match.
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