The video I’m watching about the two architectures says that Harvard architectures “can fetch instructions at the same time as reading/writing data”. This makes sense, but how is this different from pipelining? Can’t be von Neumann architectures do this as well? It also says that Von Neumann architectures follow a linear fetch, decode, execute cycle. Again, this doesn’t make sense to me. Surely pipelining means that they don’t have to do this, right?
In: 5
No, pipelining cannot fetch instructions at the same time as data.
What pipelining actually doing is reducing waste:
* it reuses idle bus cycles for fetching. Idle cycles can appear, if instruction requires some internal calculation. Multiplication, division, and read-modify-write can be donors of idle cycles. Pipeline turns `memory_time + calcualtion_time` into `max(memory_time, calculation_time)`.
* it can also allow for fractional fetch time, if the instruction machine code is shorter than the bus width. For example, 1 byte instruction on 2 byte bus can be fetched (on average) in 0.5 bus cycles.
However, pipelining cannot do two memory accesses in the same time. No miracles here. Von Neumann will always have `memory_time = fetch_time + data_time`, while Harvard can do `max(fetch_time, data_time)`.
As for a linear fetch, decode, execute cycle – no, that doesn’t seem right.
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