The video I’m watching about the two architectures says that Harvard architectures “can fetch instructions at the same time as reading/writing data”. This makes sense, but how is this different from pipelining? Can’t be von Neumann architectures do this as well? It also says that Von Neumann architectures follow a linear fetch, decode, execute cycle. Again, this doesn’t make sense to me. Surely pipelining means that they don’t have to do this, right?
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Harvard cleanly separates instruction memory from data memory, allowing access to instruction memory and data memory simultaneously. Von Neuman does not have this clean separation, just a common memory, so only 1 memory access at a time. This is commonly known as the von Neuman bottleneck.
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