The video I’m watching about the two architectures says that Harvard architectures “can fetch instructions at the same time as reading/writing data”. This makes sense, but how is this different from pipelining? Can’t be von Neumann architectures do this as well? It also says that Von Neumann architectures follow a linear fetch, decode, execute cycle. Again, this doesn’t make sense to me. Surely pipelining means that they don’t have to do this, right?
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von Neumann has a single memory with a single database for both the induction and the data.
Harvard has two separate memory systems one for the program and one for the data.
Let’s ignore cache memory and a system with multiple memory buses to a unified memory.
A von Neumann machine can’t read an induction from memory at the same time at is reads or writes data. There is only a single memory subsystem. A Harward architecture can always do that. Pipelining does not matter, it can happen at the same moment because there is only one memory bus.
Even if you have two memory buses the data and instruction can be on the same bus. So you can read instructions and data sometimes at the same time.
The advantage of von Neumann is it is cheaper. The memory is also shared and the amount use for the installation and the data depend in your requirement right now. A Harvard architecture can have full data memory, you can use the induction memory for data even if a lot of it is empty.
The advantage of Harward is it will be faster.
If you look at the computer you use right now it might look like a pure von Neumann machine. That is not the case because when you look at cache memory the Level 1 cache is typically split. AMD Zen first generation had 32KB L1 data cache, 64KB level 1 induction cache per core. It also has 512KB unified L2 and 2048 KB unified L3 cache,
So if the induction and/or data in the L1 cache it is works as a Harvard machine. But if it needs from main memory it is a von Neumann.
So desktop computers the hybrid systems the are Harward on in regards ot L1 cache and von Neumann in regards to higher cache level and main memory.
If you look at microcontrollers a Harvard architecture is more common. The induction memory is often FLASH memory and the data is in RAM. By splitting them and having them integrated on the same chip you can avoid cache memory.
Because applications are fixed in them the model you use will in part depend on the amount of memory. There is often multiple models with different amounts of memory at different price points. You usually select the cheapest model that can do the tasks you require.
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