The video I’m watching about the two architectures says that Harvard architectures “can fetch instructions at the same time as reading/writing data”. This makes sense, but how is this different from pipelining? Can’t be von Neumann architectures do this as well? It also says that Von Neumann architectures follow a linear fetch, decode, execute cycle. Again, this doesn’t make sense to me. Surely pipelining means that they don’t have to do this, right?
In: 5
I’m not exactly sure, but from the datasheet of a Harvard architecture microcontroller, this one has a separate bus and memory for code (flash memory), from RAM. This allows it to read instructions at the same time as RAM accesses. (reading constant data from flash is “slower” because of this, so constant globals will be copied to RAM in the code).
Others, use a single bus, storing both code and data in RAM.
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