The video I’m watching about the two architectures says that Harvard architectures “can fetch instructions at the same time as reading/writing data”. This makes sense, but how is this different from pipelining? Can’t be von Neumann architectures do this as well? It also says that Von Neumann architectures follow a linear fetch, decode, execute cycle. Again, this doesn’t make sense to me. Surely pipelining means that they don’t have to do this, right?
In: 5
If the execute cycle also accesses memory, then it conflicts with another instruction fetch cycle. Modern processors fetches new instructions on every cycle so they are all modified Harvard.
Latest Answers