How do chip design engineers make sure that there is no interference between different circuit modules due to electromagnetic fields, given that every circuit component is very close to each other?
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Pre-layout, timing tools use a basic line transmission model that can be altered if it is known some busses will be near each other.
Post-layout, capacitance is extracted from the metal layers and a transmission line model is fed to the same timing tools. THe use of victim/attacker analysis determines if the lines are shielded sufficiently. Often post-layout timing requires resizing of gates and possibly rerouting. The transmission model used to assume worst-case impact to noise but this became too costly and overrides were added for certain signals that weren’t running close enough to be impacted.
Metal layer rules require alternate tracks of ground between signals to additionally mitigate noise.
Design rule checkers (DRCs) tend to be run in parallel with a mock layout to make sure there isn’t a huge gap between pre and post layout.
Source: I did timing and layout most of the 1990’s.
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