How do chip design engineers make sure that there is no interference between different circuit modules due to electromagnetic fields, given that every circuit component is very close to each other?
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You have these issues at every scale of the electronics design process, even in PCB layouts. With a lot of experience, you’ll become better at gauging what works, what doesn’t, and what issues might arise. Certainly simulation is part of it, but you have to be able to start from a large knowledge base and be able to adapt some existing circuits to suit your needs.
There are a lot of general design rules, like keeping digital clock sources away from analog signals; separating digital, analog, and power grounds as well separating power supplies are usually a must. Differential signal pairs have to be routed together, which helps them cancel noise. Ground planes have to be stitched to avoid any islands. Sharp corners are a no-no for fab and current density reasons. Temperature sensitive circuits have to be kept away from power supplies. If you run out of options, you can move things to different layers, but that may be more expensive or not an option for your process.
Experimenting on silicon is more expensive than PCB, but there are ways to put some test parts on a shared wafer with other projects. There are maskless prototyping tools, but the features are pretty large. Source: designed and built some of said tools.
When a new design process is developed, they run a series of tests and simulations to determine rules for making the chips so they work properly. These are verified in test chips as well. These rules are referred to design rule checks (or DRCs).
The software used by the designers to make the chips, makes sure that the design does not violate any of these DRCs. If they do, the design is redone until all the rules are passed successfully. The software is also written to take these rules into account when automating the design process so these violations are not created.
These rules can include things like; how long wires can run next to each other, the shapes of the wires, how wide the wires need to be to connect to another wire, etc.
There can be 1000s of these rules and as the process gets smaller, the number of rules gets larger.
Pre-layout, timing tools use a basic line transmission model that can be altered if it is known some busses will be near each other.
Post-layout, capacitance is extracted from the metal layers and a transmission line model is fed to the same timing tools. THe use of victim/attacker analysis determines if the lines are shielded sufficiently. Often post-layout timing requires resizing of gates and possibly rerouting. The transmission model used to assume worst-case impact to noise but this became too costly and overrides were added for certain signals that weren’t running close enough to be impacted.
Metal layer rules require alternate tracks of ground between signals to additionally mitigate noise.
Design rule checkers (DRCs) tend to be run in parallel with a mock layout to make sure there isn’t a huge gap between pre and post layout.
Source: I did timing and layout most of the 1990’s.
1. Electricity running through traces tends to be quite “sticky”. As a rule of thumb, separating signals by 20 times the distance between the layer with the signals, and ground, is far enough that they won’t interact. Given that modern boards have a decent few layers, that could be a very short distance.
2. Put more ground in places to stop signals from leaking out.
3. Simulations.
4. A lot of designers fail at this.
This is literally most of what my career consists of. The field is called Signal Integrity, and it is the science of making electrical signals go where we want them to without excessive crosstalk and interface. We design signalling schemes and interconnect with certain features that help, like self shielding, differential signaling, special kinds of encoding that are tolerant to noise, limiting the signal slew rate to just enough to get the job done, and careful layout. I have been doing this for 25 years and use a variety of concepts that were figured out back in the days of the telegraph and have been scaled down to nanometers. Much of the work starts with fundamental calculations on a whiteboard and software and measurements are used to automate and validate. Right now I work on fiber optic laser drivers and receivers for datacenter applications with signaling speeds of over 100 Gigabit per second per data lane.
They dont really.
There are some designs that are required to protect from EM and ESD, but you cant get 100 % confidence in protection, so after that comes tests on prototypes. Even that cant give a 100% answer, because you end up testing one prototype chip, and the manufacturing process is different, meaning you also have to test chips once you start producing them with a different method.
This is why critical systems that must not fail have multiple redundancies. A critical system needs to be able to work when crippled. It does not means its parts should never break down; it means it is engineered to have the least possible failures, but if and when they happen, it still works as a whole.
Typically, modern CPU can have defects when built, so they can be partially disabled. That 12 cores CPU with a defect on 2 cores will have them disabled and will be sold as a 10 cores CPU.
A really big part of it is that they *aren’t* going in and writing out every single gate and wire by hand and then seeing if it’d work.
There are currently around as many transistors in a modern CPU than there are people alive. You just can’t do that by hand. Sure, you could try, but if you put one down every second you’d still die before a single desktop CPU was designed.
So instead for a lot of it you build up larger patterns that you’ve used before, which already do what you want, and for which you already know what kinds of fields they produce in aggregate. And then you plug them together, and make sure those connecting wires don’t mess with the stuff they’re near.
So it’s sorta like designing a city. You don’t choose what door trim shape and second floor east-facing windows’ colors will be for every house. You say “this area is residential”, estimate how many roads you need to support it and make sure they work with the roads they connect to, and then buildings happen (yay building architects) and the miniscule details about those houses don’t matter to the city planners.
EMC engineers work with voodoo magic and there are very few people in this world that are great at understanding, managing, and fixing issues that show up.
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