If there are billions of transistors in a CPU, there is no chance that somebody designed every single one of them manually. Is their layout calculated or something?
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Short answer, because the detailed one has a lot of scope creep: yes, it is all automated… but there are a lot of things you need to tell the programs to get things right.
The very simplified process (skipping a lot of steps) is as follows.
Some dudes built a set of “standard cells” (think LEGO blocks) for a specific technology (loosely a “these are the transistors” set, there are many with different tradeoffs). Each of these cells has defined characteristics, the most notable of which is its function (i.e. “what does it do”), that are all saved in a big fat database for later use. This is a gigantic simplification because you can focus on *what* to do (albeit to an extreme detail) instead of “how should I dope my silicon to do what I need”.
The guys designing a digital portion of a chip write code in specialized languages that describes in high detail, but still with higher abstraction than standard cells can provide, what the block should do. They (or someone else) then take the description and feed it to a synthesiser that tries to figure out which standard cells to use and how to connect them to do what the code requires, and thus spits out a “netlist” of cells and the wires between them. This step already is unfeasible by hand even for small blocks, small chips can easily have some tens of thousands of cells. Notice that this is somewhat like the map of a metro system: it shows how stuff is connected, but it does not really hold up as a project for construction (“the tunnel should bend there, then avoid that place, then get bigger because reasons…”) and needs to be refined further into an actual 3d model.
The final step in defining how exactly the chip will look in the real world is taking the synthesised netlist and loading it into a layout program, which is tasked with fitting all those cells in a defined space and actually making them work. You might need to have some close to each other to limit the propagation time of some signals, or the opposite in order to avoid some nasty things that can happen when calculations are ready too soon (specifics on this are out of scope). Some wires running parallel to each other might crosstalk and need to be spaced further apart or shielded. Connecting the giant bundle of wires going all over the place without having them touch each other is hard. Sometimes the program is not able to do everything right and some dude has to step in a sort things out manually if at all possible (speaking from experience, some things spook the hell out of the layout tool and you get a couple of obvious “just move this wire there” solutions that the computer cannot see by just looking at it).
If anyone is interested in how digital design works I’ll be glad to share my experience. I think I am particularly suited to provide a broad overview due to me working on small and simple chips, thus maybe missing some more advanced techniques but doing everything (RTL, simulation, linting, synthesis, formal equivalence checks, layout, timing checks, signoff, power simulation, test patterns… name it, I have done it) by myself.
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