What hurdles do we have left to get to system-on-silicon consumer devices as we already have system-on-chip today?
In: Technology
That’s a very interesting question.
A complete system needs many different silicon chips. A typical PC has a CPU chip, a GPU chip, lots of DRAM chips on the memory modules, and probably even more chips to make up the SSD.
The total area of all of those chips is enormous. Larger than what can be manufactured on one piece of silicon at this time. Basically, we can make chips that are about 800mm^2. A top of the line GPU would be about 650mm^2 which doesn’t leave a lot of room for all the other stuff.
That’s where packaging advances come into it. We can’t make one giant chip but we can combine smaller ones together in one large package or module. A Ryzen CPU is a good example of that. It has a number of CPU chips and also an I/O chip, all in one package. The CPU chips need to be fast so they are made an advanced process (i.e expensive) but the I/O chip doesn’t need to be so fast so it can be made using an older, less sophisticated, and cheaper process.
There are various ways to combine chips like that. You can place them side by side on another piece of silicon that has basically nanoscale wiring to connect things together (which is how Ryzens do it), or you can stack them on top of each other (which is a much more expensive and advanced option).
So to answer the question, I’d say the cost of combining all the chips in one package is the major hurdle. It’s a cutting edge technology and not many manufacturers can do it.
Mainly cost and flexibility. The amount of engineering work and the cost required to get everything on one piece of silicon doesn’t really make sense for most products. It is also basically impossible to reconfigure. You get what you get. If you want to use the same processor but double the memory in a future product, well…too bad. You can’t just replace the memory chip, now have to do a whole new tape-out and get another production run lined up.
Somewhat to u/wiseprecautions point, larger chip area costs more. If it costs 5 million dollars to process 1000 wafers, and you have 1,000 devices per wafer, that’s $5 per chip. If you only can fit 100 devices per wafer, that’s $50 per chip. Makes sense for a $3000 processor or a $10,000 sensor. Not so much for a $150 smartwatch.
Larger chips also lead to lower yields. Assume you have an average of 10 defects per wafer. With 1,000 devices per wafer that leads to an overall yield of 99%. With 100 per wafer that’s 90%. Your cost/chip will go up to $5.05 (+1%) in the former case, but $55.5 (+11%) in the latter case. The math isn’t quite that straightforward (defects per area would be more accurate) since multiple defects could be on the same chip, or they may not result in a functional failure, but you get the idea.
I disagree on the maximum size: you can make a chip the size of the entire wafer if you want to, but you will have serious yield loss. There are things like very large imaging sensors where you can only fit maybe 1-4 on each wafer. They are extremely expensive, and generally the way it works is that you don’t buy each *chip* for a certain price. You buy the production run for a certain price, and agree to purchase all of the good chips. If your run of giant chips cost $1 million, and you get 10 chips, you pay $100k per chip. If you get 20, you pay $50k per chip.
Larger devices are more expensive. More of the cost of running the line, of fallout, of testing, etc. is represented in each device. They will cost more. Making one large device that contains all of the required components might cost substantially more than just buying them all separately.
There’s also the issue of different process technologies. And not just different nm-sizes and the like. A MEMS accelerometer has a very different process flow and stackup than a RAM module, and now you have to accommodate *both* in a single process.
Finally, there is the intellectual property issue. OEMs will gladly sell you the raw die for their sensor or memory module so that you can incorporate it into your SoC. They’ll be somewhat less willing to give you the full chip design, which you would require to implement it yourself in silico.
It’s not necessarily that these are engineering hurdles. We *could* do it today. It’s just not worth it for most peripherals. Apple for example could easily afford to integrate all of their modules onto one piece of silicon if they really wanted to, but it doesn’t make sense to do it.
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