Shrinking circuits down any further causes too much quantum tunnelling. Basically, electrons normally stay flowing on the defined path (circuit). If those circuits are too close together, electrons can spontaneously jump across the gap through undesirable (but really cool!) quantum effects.
This limits how close the traces can be to each other, limiting how small you can shrink things. And if you don’t shrink things, you either have heat problems because of friction generated from electrons being pushed through the circuit too fast, or you end up with a chip that’s too large, causing timing, synchronicity, or speed problems.
So speed isn’t the singular attribute of performance any more. Parallelism, 3D layering, cache, and instruction additions and optimization increase performance and capability in better ways than simply “turning up the speed knob”, like we used to in years past.
Latest Answers