They are designed in hardware description languages such as Verilog and VHDL. These languages lack control flow (jumps and loops) available in software languages and the cost of operations is not like in software. For example in software “integer add” and “logical and” take the same time — one clock cycle. But in hardware “logical and” is implemented as 1-2 gates and propagation is measured in picoseconds while 16 bit integer add needs 80-400 gates depending on speed and the speed is tens times slower than “logical and.” So while you can use + in Verilog you want to avoid it. When they design a CPU they don’t use + for the arithmetic unit. They describe it using logical operators.
The languages allow you to design modules. You build and test bigger module out of smaller already tested modules. At the end they use software to translate the whole design into a graph of gates (such as NAND gates) and another software to actually layout the graph in 3D with the actual sizes of the elements specified.
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