eli5 : How does reducing cpu’s lithography help its performance? couldnt you fit more stuff into a bigger cpu?
In: Technology
In a 4 GHz processor you’re basically sending 4 billion pulses of electricity though the CPU every second. Each of those pulses can only represent one (1) instruction and you have to wait until an instruction is fully executed and leaves the CPU before sending the next.
The reason that you have to wait before sending the next instruction is that you don’t know how long its going to take for each instruction to go through or what path it will take. If you send instruction #2 in before instruction #1 has come out then you don’t know what will come out of the processor. It could be the result of instruction #1 followed by the result of instruction #2. Or it could be that instruction #2 crosses over into instruction #1 and you get an output that is the combination of both. Or you could get instruction #2 coming out first, followed by instruction #1. There’s no way to know what you got without already knowing what the result of both instructions were beforehand.
When you’re sending 4 billion instructions per second the speed of light starts to become extremely relevant, even over distances that small. The smaller the CPU, the shorter it takes each instruction to pass fully through the chip and come out the exit. The quicker instructions are exiting the chip, the faster you can send them in.
So doubling the size of a chip doesn’t double the speed – it halves it because now you have to wait twice as long for each instruction to pass through. Conversely, halving the size of a chip doubles the speed because now you have to wait half as long before sending in the next instruction. That’s why chip manufacturers make such a big deal about the nanometer size of the transistors. If you took two chips with identical architecture, but one chip used 7nm transistors while the other used 14nm transistors, the 7nm chip would be twice as fast.
Both Intel and AMD have developed some variant of multithreading technology that does try to predict the outcome of any given instruction. This, in theory, allows the chip to sometimes send in a second instruction without waiting for the first to exit. In practice, it doesn’t get to send in that second instruction very often and even under ideal conditions you’re still limited to sending in two instructions at once.
If you could send in an infinite number of instructions at once then sure, bigger might be better. But “very occasionally two” is really the practical limit and its going to be a awhile before we can push beyond that (if we ever can).
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