For example i notice that the latest chips are 3 nm & below, & over the last decade i’ve seen it shrink little by little. What is it about this process that more money needs to be poured into each die shrink, & why couldn’t we just jump from 90nm to 3nm instead pf 65nm etc etc?
In: Engineering
That’s just how technological progress works in general. Each new innovation is based off of loads of things that have also been innovated from the last iteration. To give you an extreme example, a similar question to yours would be “Why didn’t we get electric vehicles after horses and carriages and instead we had to go through steam power, then fossil fuels”.
“Shrinking” a cpu relies on very high precision equipment. At the moment a cpu is made at a certain scale, that’s the highest precision the existing tooling allows. And retooling is also insanely expensive in the chip making industry.
However, for some years now the size designation has no longer been reflective of the actual size: https://en.wikipedia.org/wiki/3_nm_process
It is economics, not just technology. What drives shrink is the cost per IC. The investments for this are huge.
Smaller circuits mean more circuits fit on a wafer (the flat disc on which chips are printed). A lot of the cost is per wafer or per die (chip), not per circuit.
A small cost reduction is not enough to offset the huge investments required for a new node.
So whether you shrink by 5% or by 50%, you still need to develop a new process, which is timely and costly. Possibly requiring new machines or a new fab. Customers are not willing to pay enough for a 5% shrink – but when you get to 30% it gets interesting.
What you are talking about is silicon die feature sizes. Making a chip involves adding thin layers on a silicon wafer. It is not that different from using a stencil to paint something. But while you might be able to cut out a stencil to within a millimeter of the intended line the chip foundries are able to do this to within a few nanometers. Each process uses new technology that have taken 10-15 years to develop. In some cases they can abandon technology while it is still only a lab experiment if it does not give the expected results, other times you end up building an entirely new foundry and start tuning the process before you notice the limits. You have examples of companies spending 15 years and billions of dollars making an entire new foundry using completely new technology to make 4nm chips only to find out it can only do 6nm chips. That would have been fine if they had started 10 years earlier. But now it is kind of a huge waste of money. And just imagine all the projects which were dropped after a decade of research because they could not deliver what they hoped. It was easier when they were aiming for 65nm.
And just for reference the silicon atom is about 0.1nm thick. So when they make a chip forge with a 3nm feature size that means they can place an atom to within 30 atoms accuracy within a die that is billions of atoms across.
It takes lots of research how to make such chips. You need to engineer a method to actually carve such extremely fine structures into silicon, depositing some other elements in very controlled doses, and so on.
This process for example involves making and focusing light (or electrons) with very high precision. Light cannot really act with much more precision than roughly its wavelength. So to make smaller and smaller structures we need light to be of a rather short wavelength, entering into UV or even x-ray territory.
Creating consistent and _coherent_ UV light is already not so easy. At some point even lenses don’t work anymore for various reasons. X-rays in particular cannot really be treated as visible light at all, they bend around every corner and are not really reflected the way mirror does, regardless how flat and perfect a surface is. Instead they go everywhere and things get complicated.
As mentioned we can sometimes instead use electron beams. But this just adds new issues. We have to replace any lenses and mirrors by electric and magnetic fields and such!
Other aspects that had a lot of development are for example the _architecture_ (how and what things are arranged on the chips) and the general abilities (multiple cores and threads, graphics support on some CPUs, tensor and other such developments on graphics card, …). Those all aren’t just minor changes but are extremely complex to optimize.
With the sizes we are now at (3 nm is ~30 atoms in diameter!) it even matters that electrons tunnel by quantum “magic” by the way.
The above and many other **technologies simply had to be invented first, which takes time**. It is also easier to slowly improve and thus test each progressive step without changing too much else. For example Intel alternates: each second generation decreases in size, while the other iterations focus on the architecture. It would make little sense to wait literally 10 or 20 years until we finally decrease in size, chip factories have to be refined and improved long before that to keep up with developments.
That little word “just” is doing a whoooooole lot of heavy lifting. 20 years and hundreds of billions if not trillions of dollars worth of research and manufacturing development. It’s not economically viable to spend 20 years bringing a product to market, so instead you bring something new and improved to market every few years to ensure revenue generation even if you know it’s not the theoretical best thing you could possibly do given another decade of work.
While the technical statements on the other comments are true enough, I was surprised to learn that, for example, “[the 14 nm process](https://en.wikipedia.org/wiki/14_nm_process)” is just a marketing term. From the article “Since at least 1997, “process nodes” have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit”.
So a large part of why they jumped from 90 nm to 65 nm (in 2005, so more recent than 1997) was because the marketing people thought it sounded cool.
every time a new smaller process size starts the number of defects is high. yield can drop from a mature process at >99% all the way to 10%. this is quickly worked back up to profitable levels but will fully take several months to a year where the die yield per wafer equals what was possible before.
this is because the new defects need to be characterised and rooted out iteratively. e.g. etch for 1 more second, increase plasma voltage by 5%, polish by 10 angstroms less, whatever it may be, depending on the defect.
a good shrink can get you breakeven at 70% yield compared to the previous process at 99% yield. anything above is better gross margins.
the real profits from the change come from Year 2 onwards to whenever it reaches end of life and the next jump begins. some companies do 4 year cycles, some faster some slower.
the time to develop the next jump is also longer than the time it takes to perfect it during manufacturing. design work on the next step can begin even before the current step has qualified and started low volume manufacturing.
There is a sweet spot to manage this whereby you want to keep improving technology at a steady rate but don’t want to hit the next jump before you have perfected the current step. in that sense you want to keep competing with other providers but do not want to bite off more than you can chew.
First of all, the terms like 65nm, 32nm, 10nm, 3nm, etc., are purely marketing (fictional) terms which are a bit misleading. They no longer represent actual feature sizes like gate length or pitch. E.g., in the 3nm process actually has a gate pitch of ~ 48nm, and the upcoming 2nm process has a gate pitch of ~ 45nm.
At some point the industry should have just called it “generations” like 10th gen, 11th gen, 12th gen, etc.
So your question is like asking “why didn’t we just jump from the 10th generation to the 15th generation in one step?” Well, each generation has a ton of science, technology, engineering, financial, intellectual property licensing and sometimes even political considerations that needed years to be solved.
For example, conventional lithography uses optical light (at 193nm) but the new processes especially for 3nm and below will increasingly require extreme ultraviolet lithography (EUV) at 13.5nm. Currently there’s only one company in the world (ASML) that’s even capable of making EUV systems, and the technology behind it is considered so sensitive that it has national security implications.
because we work really hard for a few years. say hurray we made a 30% improvement and then start making a product. If we worked really hard for a few years and make 30% improvement and then don’t make a product then we don’t have the money to work a few more years to get another 30% improvement. In the extreme, if I had infinite money I could work my entire life and make massive improvements that would never become products and probably die with me because they were never distributed to people who want to steal the improvements to make their own products.
if your question is why don’t we just make the move from 90nm to 3nm is 3 years, it is because we don’t know how. Why didn’t you earn a 6 figure salary by your 3rd birthday? You didn’t know how.
If you are asking what physically is stopping us? Diffraction and the properties of materials. Light doesn’t go where we want it to go. We usually try and make it go with materials, but no known materials make it do what we want it to do.
At its most basic, picture spray painting or roller paining though a stencil. Although I’m not sure a five year old would know stencils it still conforms to ELI5. As your stencil gets smaller you can fit more readable text in a small area. Naturally the formulation of the paint and the stencil materials will need to change as you approach a theoretical minimum sized hole for the paint to get through. The people who make the paint and the stenciling machine are constantly engineering the next version to make the holes smaller, and fit more. The spend tens of billions in development stages both making it happen in lab then converting the lab to a usable assembly line process . 7 nm vs 3 nm are analogous to the micro droplet of “paint” (doped silicon) that can be effectively deposited in the right location that eventually though enough deposit layers becomes a field effect transistor.
Latest Answers