For example i notice that the latest chips are 3 nm & below, & over the last decade i’ve seen it shrink little by little. What is it about this process that more money needs to be poured into each die shrink, & why couldn’t we just jump from 90nm to 3nm instead pf 65nm etc etc?
In: Engineering
At its most basic, picture spray painting or roller paining though a stencil. Although I’m not sure a five year old would know stencils it still conforms to ELI5. As your stencil gets smaller you can fit more readable text in a small area. Naturally the formulation of the paint and the stencil materials will need to change as you approach a theoretical minimum sized hole for the paint to get through. The people who make the paint and the stenciling machine are constantly engineering the next version to make the holes smaller, and fit more. The spend tens of billions in development stages both making it happen in lab then converting the lab to a usable assembly line process . 7 nm vs 3 nm are analogous to the micro droplet of “paint” (doped silicon) that can be effectively deposited in the right location that eventually though enough deposit layers becomes a field effect transistor.
Latest Answers