For example i notice that the latest chips are 3 nm & below, & over the last decade i’ve seen it shrink little by little. What is it about this process that more money needs to be poured into each die shrink, & why couldn’t we just jump from 90nm to 3nm instead pf 65nm etc etc?
In: Engineering
What you are talking about is silicon die feature sizes. Making a chip involves adding thin layers on a silicon wafer. It is not that different from using a stencil to paint something. But while you might be able to cut out a stencil to within a millimeter of the intended line the chip foundries are able to do this to within a few nanometers. Each process uses new technology that have taken 10-15 years to develop. In some cases they can abandon technology while it is still only a lab experiment if it does not give the expected results, other times you end up building an entirely new foundry and start tuning the process before you notice the limits. You have examples of companies spending 15 years and billions of dollars making an entire new foundry using completely new technology to make 4nm chips only to find out it can only do 6nm chips. That would have been fine if they had started 10 years earlier. But now it is kind of a huge waste of money. And just imagine all the projects which were dropped after a decade of research because they could not deliver what they hoped. It was easier when they were aiming for 65nm.
And just for reference the silicon atom is about 0.1nm thick. So when they make a chip forge with a 3nm feature size that means they can place an atom to within 30 atoms accuracy within a die that is billions of atoms across.
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