MIPS was one of the first RISC architectures around. It was heavily pipelined which let it keep up a 1 instruction per cycle execution rate and claw back performance against its CISC competitors. Also, because of the simplicity of the architecture and the lack of complexity in the wiring of the ICs it could scale to high frequencies on similar process nodes.
For instance, the R4000 was released at the start of 1993 starting at 100MHz on the 0.6um (600nm) process node while Intel was struggling to get the 66MHz P5 out the door. By 1994 Toshiba had a 200MHz part fabbed on 0.3um (300nm) while Intel was struggling to get its 75MHz P54C parts out the door.
Because of the predictable in-order pipeline and the 1 clock instruction latency they still make great embedded CPUs. The compiler can make sure metrics for realtime programming are met far easier than with a machine that has weird instructions that can take dozens of cycles.
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