What is CISC Architecture?

Question

I have studied ArmV8, which is RISC architecture before. I know the assembly, and the pipelining, data forwarding, and other data hazard solutions like stalling and branch prediction.

But what is exactly is CISC? Like what does x86 assembly look like? Do things like pipelining, data forwarding still exist? If yes, then what exactly is the difference between RISC and CISC?

In: 4

Answer 1

The difference is in the instruction ser and how complex instruction exits. An ARM add operation only adds two registers.

X86 can add can be done on registers but you can have constant and memory access to like

addb $10, (%eax) —–add 10 to the single byte stored at memory address stored in EAX

This is a multiple operation on ARM. So simple instruction vs complex instruction.

So you would have a complex multi-cycle execution of that instruction on an old x86 CPU where it executed microcode for that CISC instruction. But if you look at a x86 CPU today complex instructions are broken down into multiple Micro-operation that is like the RISC operation an ARM executes. This was introduced in the mid-1990.

Look at how AMD describes the [ZEN microachicture](https://cdn.wccftech.com/wp-content/uploads/2016/08/AMD-Zen_Microarchitecture.png) where instructions are decoded into Micro-op and they are the ones that is executed.

ARM is not a pure RISC like its original idea of it in the 1970s. x86 might look like CISC but that is the instruction you send to the CPU not what is executed it do on the fly translation to an internal operation that you would call RISC if you could see them.

So CISC vS RISC is today about what is exposed to the outside not how the internals is designed.

What is better? The answer is it depends. The micro-operation are internal for that CPU and the next model can have a change micro-operation instruction set. You can change it if you find a way to do it better. The machine code can be shorter with CISC than RISC for the same program. So the less memory bandwidth is used to transfer them and the cache memory can contain a larger part of the program.

There is drawbacks. You need the extra hardware to create the micro-operation and then recombine the result. That result in higher power usage.