What is CISC Architecture?

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I have studied ArmV8, which is RISC architecture before. I know the assembly, and the pipelining, data forwarding, and other data hazard solutions like stalling and branch prediction.

But what is exactly is CISC? Like what does x86 assembly look like? Do things like pipelining, data forwarding still exist? If yes, then what exactly is the difference between RISC and CISC?

In: 4

RISC and CISC are more…”philosophies” than real hard computer science elements.

RISC aims for simplicity of language. Fewer instructions but executed faster. (One instruction per clock cycle if I remember correctly)

CISC aims for simplicity of code. Many instructions, allowing written code to be smaller, but not executed as fast.

As for the specifics of x86. Phew…I am definitely not the person to help you there. I sat down with x86 assembly once and noped out. Admittedly my experience is entirely 6502 so even ARM would be a challenge I feel.

The difference is in the instruction ser and how complex instruction exits. An ARM add operation only adds two registers.

X86 can add can be done on registers but you can have constant and memory access to like

addb $10, (%eax) —–add 10 to the single byte stored at memory address stored in EAX

This is a multiple operation on ARM. So simple instruction vs complex instruction.

So you would have a complex multi-cycle execution of that instruction on an old x86 CPU where it executed microcode for that CISC instruction. But if you look at a x86 CPU today complex instructions are broken down into multiple Micro-operation that is like the RISC operation an ARM executes. This was introduced in the mid-1990.

Look at how AMD describes the [ZEN microachicture](https://cdn.wccftech.com/wp-content/uploads/2016/08/AMD-Zen_Microarchitecture.png) where instructions are decoded into Micro-op and they are the ones that is executed.

ARM is not a pure RISC like its original idea of it in the 1970s. x86 might look like CISC but that is the instruction you send to the CPU not what is executed it do on the fly translation to an internal operation that you would call RISC if you could see them.

So CISC vS RISC is today about what is exposed to the outside not how the internals is designed.

What is better? The answer is it depends. The micro-operation are internal for that CPU and the next model can have a change micro-operation instruction set. You can change it if you find a way to do it better. The machine code can be shorter with CISC than RISC for the same program. So the less memory bandwidth is used to transfer them and the cache memory can contain a larger part of the program.

There is drawbacks. You need the extra hardware to create the micro-operation and then recombine the result. That result in higher power usage.

RISC cpus will use simpler instructions. But internally, there’s not as much difference.

Basic Load/Store operations, Arithmetic, etc. Arithmetic operations operate only on registers.

On ARM:

ldr r1, [r4]
ldr r2, [r4+4]
add r0, r1, r2
str r0, [r5]

loads two values from memory,
adds registers r1 + r2 and stores to r0, then stores that to memory

x86 has different addressing modes, you can do register-register, register-memory, memory-register

it would look more like:

mov eax, [rbx]
add eax, [rbx+4]
mov [rdx], eax

So x86 saves an instruction, but internally it’s still executing similar lower-level instructions (microcode).

Yes pipelining, instruction reordering, etc definitely occur on CISC/x86 as well.